1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various methods of forming strained channel regions on FinFET devices by performing a heating process on a heat-expandable material.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each transistor device comprises laterally spaced apart drain and source regions that are formed in a semiconductor substrate, a gate electrode structure positioned above the substrate and between the source/drain regions, and a gate insulation layer positioned between the gate electrode and the substrate. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region and current flows from the source region to the drain region.
A conventional FET is a planar device wherein the entire channel region of the device is formed parallel and slightly below the planar upper surface of the semiconducting substrate. To improve the operating speed of planar FETs, and to increase the density of planar FETs on an integrated circuit product, device designers have greatly reduced the physical size of planar FETs over the past decades. More specifically, the channel length of planar FETs has been significantly decreased, which has resulted in improving the switching speed and in lowering operation currents and voltages of planar FETs. However, decreasing the channel length of a planar FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the planar FET as an active switch is degraded.
In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1 is a perspective view of an illustrative prior art FinFET semiconductor device 100 that is formed above a semiconductor substrate 102 wherein the fins 114 of the device 100 are made of the material of the substrate 102, e.g., silicon. The device 100 includes a plurality of trenches 113, three illustrative fins 114, a gate structure 116, a sidewall spacer 118 and a gate cap layer 120. An isolation material 117 positioned in the trenches 113 determines the active portions of the fins 114 that contribute to electrical activity. The gate structure 116 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material, and one or more conductive material layers that serve as the gate electrode for the device 100. The fins 114 have a three dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device 100 when it is operational. The portions of the fins 114 covered by the gate structure 116 are the channel regions of the FinFET device 100. The portions of the fins 114 that are positioned outside of the spacers 118 will become part of the source/drain regions of the device 100.
In the FinFET device 100, the gate structure 116 encloses both sides and the upper surface of the fins 114 to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fins 114 and the FinFET device only has a dual-gate structure (sidewalls only). Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to increase the drive current per footprint of the device. Also, in a FinFET, the improved gate control through multiple gates on a narrow, fully-depleted semiconductor fin significantly reduces the short channel effects. When an appropriate voltage is applied to the gate electrode 116 of a FinFET device 100, the surfaces (and the inner portion near the surface) of the fins 114, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance, capability and reliability of such devices. One method that has been employed to improve the performance of FinFET devices involves imparting a desired strain on the channel region of the device to enhance device performance so as to increase the mobility of charge carriers, e.g., electrons or holes, depending upon the type of device under construction. More specifically, a tensile strain is induced on the channel region of an N-type FinFET device to improve its performance, while a compressive strain is induced on the channel region of a P-type FinFET device to improve its performance. One particular technique used to create such desired strain conditions in the channel region of the devices involves, after forming the gate structure, removing a portion of the fins in the source/drain region and replacing the removed portions of the fins with a different semiconductor material (e.g., SiGe, Ge and SiC materials) that has a different lattice constant than that of the original fins. This replacement semiconductor material is normally formed by performing one or more selective epi deposition processes. As a result of the addition of the lattice mismatched materials in the source/drain regions, a desired strain—tensile or compressive—may be induced on the channel region of the device.
Unfortunately, as device dimensions continue to decrease, and particularly as the gate pitch of the devices continues to decrease, there is very little volume of the lattice mismatched materials in the source/drain regions. As a result, the strain induced by the relatively small amount of the lattice mismatched materials in the source/drain regions may be less than effective in creating the desired amount of strain on the channel region and the strain that is induced may not be as stable or permanent as would otherwise be desired.
The present disclosure is directed to various methods of forming strained channel regions on FinFET devices on integrated circuit products by performing a heating process on a heat-expandable material that may solve or reduce one or more of the problems identified above.